The present invention relates to a logic circuit provided with a scan circuit for facilitating a diagnosis of the logic circuit.
In order to improve the testability of a large-scale logic circuit, a method has been used in which a scan path is added to a large-scale complicated sequential circuit, and the sequential circuit is divided into a plurality of small-scale combinational circuits each connected between latches. This method will be explained below, by reference to the drawings.
FIG. 1 shows an example of a sequential circuit which is to be tested. A sequential circuit can be divided into a plurality of partial circuits each including no latch (that is, combinational circuits) and a plurality of latches. In FIG. 1, reference numerals 100, 110 and 120 designate combinational circuits, 201 to 203 latches, 710, 720 and 730 system input terminals for applying input data to a sequential circuit 1, and 740 a system output terminal for delivering output data from the sequential circuit 1. When system clock signals C.sub.i (where i=1, 2 and 3) are put to an ON state, the latches 201 to 203 take in and hold system data D.sub.i (where i=1, 2 and 3) inputted thereto. The combinational circuits 100, 110 and 120 are applied with system data from the input terminals 720 and 730, system data from the latch 201, and system data from the latches 202 and 203, respectively, and deliver system data corresponding to input system data to the latch 202, the latch 203, and the system output terminal 740, respectively. In more detail, the first combinational circuit 100 receives data D.sub.0 and D.sub.0 ' from the input terminals 720 and 730, the second combinational circuit 110 receives the output data D.sub.1 of the latch 201, and the third combinational circuit 120 receives the output data D.sub.2 and D.sub.3 from the latches 202 and 203. In the sequential circuit 1, the result D.sub.i (where i=2 or 3) of logical operation performed by each combinational circuit 100 or 110 is stored in the latch on the output side of the combinational circuit in response to the clock signal C.sub.i (where i=2 or 3), and then sent to a succeeding conbinational circuit. Thus, a predetermined output signal D.sub.4 corresponding to the input signals applied to the system input terminals 710, 720 and 730 is obtained at the system output terminal 740. Even when the sequential circuit 1 includes a feedback loop, the circuit 1 can operate in a manner similar to that described above. As the number of logic gates existing between the system input terminals 710, 720 and 730 and the system output terminal 740 is larger, it becomes difficult to detect a fault in the sequential circuit 1.
In order to solve the above problem, a scan-path method has been widely used. In this method, an access path for easily observing and controlling a latch, is additionally connected to each of latches included in a sequential circuit. By doing so, each latch can be treated as a system input terminal or system output terminal, and thus the whole of the sequential circuit can be divided into a plurality of combinational circuits. Accordingly, it becomes very easy to test the sequential circuit. Two typical examples of the scan-path method have been known, one of which is a shift-scan method described in an article entitled "A Logic Design Structure for LSI Testing " (DA Conference, 1977, pages 462 to 468), and the other is a random-scan method described in an article entitled "Testing VLSI with Random Access Scan" (COMPCON, 1980, pages 50 to 52).
FIG. 2 shows an example of a circuit configuration for performing the shift-scan method. Referring to FIG. 2, latches 211 to 213 each having a scan function are used in place of the latches 201 to 203 of FIG. 1. Each of the latches 211 to 213 is made up of an L1-latch 211A, 212A or 213A and an L2-latch 211B, 212B or 213B. Like the latches 201 to 203 of FIG. 1, each of the L1-latches 211A, 212A and 213A takes in and holds system data D.sub.1, D.sub.2 or D.sub.3 when the system clock signal C.sub.1, C.sub.2 or C.sub.3 is put to the ON-state. Further, when a shift clock signal A is put to an ON-state, the L1-latches 211A, 212A and 213A take in and hold an input 270-1 from a scan-in pin SI, an output 270-2 from the L2-latch 211B, and an output 270-3 from the L2-latch 212B, respectively. The L2-latches 211B, 212B and 213B are provided for stabilizing a shift operation which will be explained below. When a shift clock signal B is put to an ON-state, the L2-latches 211B, 212B and 213B take in and hold the outputs of the L1-latches 211A, 212A and 213A, respectively. Accordingly, the L1-latches 211A, 212A and 213A and the L2-latches 211B, 212B and 213B are connected so as to form a shift string between the scan-in pin SI and a scan-out pin SO. In a diagnosis mode, by applying shift clock pulses A and B alternately, a desired value from the scan-in pin SI can be set in the latches 211, 212 and 213, and the contents of these latches can be observed at the scan-out pin SO. In a regular mode, by keeping the clock signals A and B at an OFF-state throughout the operation, the circuit of FIG. 2 can perform entirely the same operation as the circuit of FIG. 1. That is, the L1-latches 211A, 212A and 213A correspond to the latches 201 to 203 of FIG. 1, and the L2-latches 211B, 212B and 213B act as insulating elements.
FIG. 3 shows an example of a circuit configuration for performing the random-scan method. Referring to FIG. 3, latches 221 to 223 each having a scanning function are substituted for the latches 201 to 203 of FIG. 1, and are assigned respective addresses. Like the latches 201 to 203, each of the latches 221 to 223 takes in and holds system data D.sub.i (where i=1, 2 or 3) when the system clock signal C.sub.i (where i=1, 2 or 3) is put to the ON-state. Additionally, each of the latches 221 to 223 can take in and hold a value 280 from the scan-in pin SI, when the latch is selected and the scan clock signal A is put to the ON-state. Further, when each of the latches 221 to 223 is selected, the contents of the selected latch can be observed at the scan-out pin SO. An address pin AD and an address decoder 300 are additionally provided to select a desired one of the latches 221 to 223. Selection signals 302-1, 302-2 and 302-3 which are produced by decoding addresses by the address decoder 300, are sent to the latches 221, 222 and 223, respectively. Each selection signal 302-i (where i=1, 2 or 3) is ANDed with the scan clock signal A to form a clock signal for diagnosis, and is also ANDed with the output of a corresponding latch 221, 222 or 223 to form a scan-out signal. The scan-out signals from all the latches 221 to 223 are ORed by a gate 330, the output of which can be observed at the scan-out pin SO. In a diagnosis mode, a value from the scan-in pin SI can be set in a desired one of the latches 221 to 223 by applying the address of the desired latch to the address decoder 300 through the address pin AD and by applying the scan clock pulse A, and the contents of a desired latch 221, 222 or 223 can be observed at the scan-out pin SO by applying the address of this latch to the address decoder 300 without applying the scan clock pulse A. In a regular mode, by keeping the scan clock signal A at the OFF-state through the operation, the circuit of FIG. 3 can perform entirely the same operation as the circuit of FIG. 1.
As can be seen from FIGS. 2 and 3, in a sequential circuit having a scan path, each of combinational circuits which are obtained by dividing the sequential circuit in the above-mentioned manner, can be tested in the following manner.
(1) A test pattern is set in (or scanned in) a latch which is connected to the input side of a desired combinational circuit.
(2) A system clock signal for a latch which is connected to the output side of the combinational circuit, is applied to latch system data by the latch on the output side. This is called the clock advance.
(3) The system data stored in the latch on the output side is read out (or scanned out) and compared with an expected value.
The above processing is repeated for all test patterns and for all combinational circuits. In order to accurately carry out the above testing operation, several restrictions are usually placed on the logical design of a sequential circuit. One of the restrictions is to forbid the transfer of data between latches having the same phase. That is, the system clock signal for the latch on the output side is inhibited from being in phase with the system clock for the latch on the input side. For example, the system clock signal C.sub.1 applied to the L1-latch 211A of FIG. 2 and the system clock signal C.sub.3 applied to the L1-latch 213A are inhibited from being in phase. Further, referring to FIG. 3, the system clock signal C.sub.1 for the latch 221 is inhibited from being in phase with the system clock signal C.sub.3 for the latch 223. This is because a value previously set in the latch on the input side may vary in a clock advance period and thus there is a danger of the latch on the output side taking in a new value, that is, a stable operation is not always performed. The above phenomenon is based upon the fact that the width of the system clock pulse used in a diagnostic operation is larger than the width of the system clock pulse used in a regular operation, and exceeds a minimum delay time caused by a combinational circuit connected between latches having the same phase. In other words, in a case where the width of the system clock pulse is shorter than the above minimum delay time, the system clock pulse is extinguished in a time necessary for the new value of the latch on the input side to reach the latch on the output side, and thus the latch on the output side can take in the value which is previously set in the latch on the input side, without being affected by the new value. While, in a case where the width of the system clock pulse is longer than the minimum delay time, the system clock pulse may exist even after the new value of the latch on the input side has reached the latch on the output side, and thus the value which is previously set in the latch on the input side, will be lost. Also, a one-latch loop in which the output of a latch is applied to the input thereof without passing through another latch, is inhibited from transmitting data for the same reason as in the case where data is transferred between latches having the same phase.
In one of conventional methods for eliminating the above restriction on the logical design, each of the latches 211 to 213 of FIG. 2 has a master-slave arrangement and each slave latch is controlled by a clock signal for diagnosis, as shown in FIG. 6 of an article written in Japanese (NIKKEI ELECTRONICS, No. 210, 1979, pages 57 to 79).
FIG. 4 shows an example of a circuit configuration for carrying out the above method. Referring to FIG. 4, the outputs of master latches (namely, L1-latches) 211A, 212A and 213A are not used as system data and the outputs 270-2, 270-3 and 270-4 of slave latches (namely, L2-latches) 211B, 212B and 213B are used as the system data D.sub.i. Accordingly, in order to send the data of a preceding combinational circuit, for example, the data D.sub.3 of the combinational circuit 110 to the succeeding combinational circuit 120, it is necessary to fetch the data D.sub.3 of the combinational circuit 110 into the L1-latch 213A by advancing the system clock signal C.sub.3 and to transfer the data D.sub.3 from the L1-latch 213A to the L2-latch 213B by applying the shift clock signal B. The shift clock signal B is used in both a regular operation and a diagnostic operation. According to such a circuit configuration, even when the system clock signal C.sub.1 for the latch 211 is in phase with the system clock signal C.sub.3 for the latch 213, the above-mentioned problem does not arise. This is because, if the system clock signal C.sub.1 is advanced simultaneously with the system clock signal C.sub.3, the output of the L1-latch 211A may vary in accordance with a logical value at the system input terminal 710 but the output of the L2-latch 211B will be kept unchanged since the shift clock signal B is kept at the OFF-state, and thus the output of the second combinational circuit 110 will also be kept unchanged. In a sequential circuit having the master-slave arrangement, however, two kinds of clock signals C.sub.i and B are used for transmitting data in a regular operation. Accordingly, the sequential circuit has a disadvantage that the system delay in a regular operation increases and thus the operation speed of the circuit is degraded. For example, the path delay in the signal path which starts from the system data input terminal of the latch 211 and terminates at the system data input terminal of the latch 213, increases as compared with the circuit configuration of FIG. 2, by a delay time due to the L2-latch 211B of the latch 211.
In other words, a trade-off exists between the relaxation of restriction on logical design and the improvement of operation speed, and it is difficult for a conventional scan circuit to satisfy two requirements, that is, the relaxation of the above restriction and the improvement of operation speed.